"Efficient Time-Interleaved Analog-to-Digital Converters"
- Borivoje Nikolic, Professor, University of California, Berkeley
While time interleaving has been introduced as a method to overcome inherent speed limitation in earlier CMOS technologies, nowadays it is primarily being used to enable higher energy efficiency of high-data rate analog-to-digital converters (ADCs). High efficiency is obtained by both designing efficient ADCs themselves and by having a low interleaving overhead. This tutorial presents design techniques for minimizing the overhead of calibration of timing and bandwidth mismatches, necessary for minimizing the interleaving artifacts. Design examples of interleaved pipeline and SAR converters will be presented.