"Flexible Clock Generation with Low Phase Error at High Power Efficiency"
- Eric Klumperink, University Twente
Clock generation with low timing or phase error is of critical importance for many applications, e.g. radio communication links and high speed high resolution A/D conversion. Multi-phase clocks may also be required, e.g. for time-interleaved ADCs or multi-phase harmonic rejection mixers. To cover different applications and allow for programmability in multi-standard or software defined radio applications, a flexibly programmable clock frequency is desired. To achieve this flexibility, digital intensive architectures are highly preferred, where frequency dividers play a key role. Despite their "digital" nature, an analog design view is crucial to achieve low phase error and phase noise. Both phase mismatch and phase noise can be improved by admittance scaling at the cost of power consumption. To benchmarks circuits and improve their phase accuracy in a power efficient way, it makes sense to define a Figure of Merit (FoM) that normalizes for this admittance level scaling effect. Based on this Jitter-Power FoM several approaches for clock generation will be discussed, with special focus on PLLs exploiting a sampling phase detector and Multi-phase clock generation architectures (DLL, Shift Register).